It is known in the art to couple a CCD serial register and associated CCD parallel registers to store and move charge packets corresponding to either analog or digital data. Such prior art devices typically employ either a two-level or a three-level structure to allow overlapping of successive serial electrodes and parallel electrodes and to thereby provide a means to move charge packets across the surface of a silicon substrate.
The two overlapping layers or levels of parallel and serial electrode elements are typically made of conductive polycrystalline silicon and the levels are separated by thin oxide layers. In addition, the bottom-most electrode level is also typically separated from the silicon substrate by a thin oxide layer.
Multi-phase, multi-level charge coupled devices typically employ a thick oxide isolation layer to separate parallel charge transfer channels on the parallel electrodes of the parallel registers. Such thick oxide isolation regions are typically extended into the parallel-serial interface portion of the CCD device to define interface charge transfer channels having widths that are substantially less than the widths of their corresponding parallel charge transfer channels.
The channel narrowing at the interface in prior art devices is caused by a portion of the extended thick oxide isolation region that is used to isolate the parallel electrode at the interface from corresponding serial electrodes that are positioned on the same level. The constricted interface charge transfer channels are undesirable for the reason that the narrow channels reduce the speed at which charge packets cross the interface and thereby reduce the charge transfer efficiency at the interface.
The U.S. patent to Hartsell et al., U.S. Pat. No. 3,946,421 is an example of such a multi-phase, double-level metal charge coupled device having clock phase distribution electrodes positioned apart from the parallel-serial interface and utilizing a plurality of interface channels with widths substantially less than the widths of the corresponding parallel channels of the device.
Other known CCD devices utilize clock phase distribution electrodes that are positioned between the parallel and serial registers of the device. However, the devices have also employed interface charge transfer channels of reduced width. Such devices are disclosed in "IEEE Transactions on Electron Devices, Parallel Signal Injection in a CCD Using an Integrated Optical Channel Waveguide Array," Vol. ED-25, No. 2, February 1978.
Accordingly, it is an object of the invention to provide a multi-phase, multi-level series-parallel charge coupled device having interface charge transfer channels with widths substantially the same as the widths of the associated parallel charge transfer channels.
A further object of the invention is to provide such a CCD device having serial gating electrodes disposed at the interface between the parallel CCD registers and the corresponding serial CCD register.
Another object of the invention is to provide a CCD device having thick oxide isolation regions for defining parallel charge transfer channels and interface charge transfer channels of substantially the same width, the thick oxide isolation regions being substantially the same width as a single serial electrode of the serial register.
These and other objects of this invention will become apparent from a review of the detailed specification which follows and a consideration of the accompanying drawings.